In the fabrication of semiconductor integrated circuits, metal conductor lines are used to interconnect the multiple components in device circuits on a semiconductor wafer. A general process used in the deposition of metal conductor line patterns on semiconductor wafers includes deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal conductor line pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked conductor line pattern; and removing the mask layer typically using reactive plasma and chlorine gas, thereby exposing the top surface of the metal conductor lines. Typically, multiple alternating layers of electrically conductive and insulative materials are sequentially deposited on the wafer substrate, and conductive layers at different levels on the wafer may be electrically connected to each other by etching vias, or openings, in the insulative layers and filling the vias using aluminum, tungsten or other metal to establish electrical connection between the conductive layers.
Electrochemical deposition or electrochemical plating of metals on wafer substrates has recently been identified as a promising technique for depositing conductive layers on the substrates in the manufacture of integrated circuits and flat panel displays. Such electrodeposition processes have been used to achieve deposition of the copper or other metal layer with a smooth, level or uniform top surface. Consequently, much effort is currently focused on the design of electroplating hardware and chemistry to achieve high-quality films or layers which are uniform across the entire surface of the substrates and which are capable of filling or conforming to very small device features. Copper has been found to be particularly advantageous as an electroplating metal.
Copper provides several advantages over aluminum when used in integrated circuit (IC) applications. Copper is less electrically resistive than aluminum and is thus capable of higher frequencies of operation. Furthermore, copper is more resistant to electromigration (EM) than is aluminum. This provides an overall enhancement in the reliability of semiconductor devices because circuits which have higher current densities and/or lower resistance to EM have a tendency to develop voids or open circuits in their metallic interconnects. These voids or open circuits may cause device failure or burn-in.
A typical standard or conventional electroplating system for depositing a metal such as copper onto a semiconductor wafer includes a standard electroplating cell having an adjustable current source, a bath container which holds an electrolyte solution (typically acid copper sulfate solution), and a copper anode and a cathode immersed in the electrolyte solution. The cathode is the semiconductor wafer that is to be electroplated with metal. Both the anode and the semiconductor wafer/cathode are connected to the current source by means of suitable wiring. The electrolyte solution may include additives for filling of submicron features and leveling the surface of the copper electroplated on the wafer. An electrolyte holding tank may further be connected to the bath container for the addition of extra electrolyte solution to the bath container.
In operation of the electroplating system, the current source applies a selected voltage potential typically at room temperature between the anode and the cathode/wafer. This potential creates a magnetic field around the anode and the cathode/wafer, which magnetic field affects the distribution of the copper ions in the bath. In a typical copper electroplating application, a voltage potential of about 2 volts may be applied for about 2 minutes, and a current of about 4.5 amps flows between the anode and the cathode/wafer. Consequently, copper is oxidized at the anode as electrons from the copper anode and reduce the ionic copper in the copper sulfate solution bath to form a copper electroplate at the interface between the cathode/wafer and the copper sulfate bath.
The copper oxidation reaction which takes place at the anode is illustrated by the following reaction equation:Cu→Cu+++2e−
The oxidized copper cation reaction product forms ionic copper sulfate in solution with the sulfate anion in the bath 20:Cu+++SO4−−→Cu++SO4−−
At the cathode/wafer, the electrons harvested from the anode flowed through the wiring reduce copper cations in solution in the copper sulfate bath to electroplate the reduced copper onto the cathode/wafer:Cu+++2e−→Cu
In an electropolishing process, an electroplated metal is removed from a substrate. Therefore, the wafer becomes the anode and the electroplated metal on the wafer is oxidized to form metal cations. The metal cations enter the electrolyte solution and are reduced and electroplated onto the cathode.
A typical conventional electrochemical plating apparatus 10 is shown in FIG. 1. The apparatus 10 includes a tank 12 which contains an electroplating electrolyte solution (not shown). An anode 14 and a cathode 16, which is the wafer to be electroplated with metal from the anode 14, are immersed in the solution. The anode 14 typically has a planar surface 14a. 
During an electroplating process, metal from the anode 14 is electroplated onto the cathode/wafer 16 as electroplated metal 18. However, the planar surface 14a of the anode 14 causes non-uniform current distribution in the tank 12, with current field lines concentrated at the edge regions relative to the center regions of the cathode/wafer 16. This results in a higher deposition rate at the edge regions relative to the center regions of the cathode/wafer 16, forming excess metal 19 at the edges of the cathode/wafer 16. This, in turn, leads to overpolishing burden during subsequent CMP processing. Furthermore, non-uniform grain sizes between the wafer edges and center as a result of electroplating may degrade the EM or SM reliability.
One of the methods used to correct the non-uniform deposition of metal on a cathode/wafer has included the use of post-electroplating edge bead removal (EBR) processes. A common drawback of this method, however, is that EBR processes eliminate usable die areas on the wafer (about 2-5 mm for 8″ wafers). Other methods have included enhancing CMP uniformity and controlling electroplating current distribution by sheltering (applied ECP). However, these methods have shown limited effectiveness.
Copper electropolishing (EP) has been regarded as a possible candidate for replacement of copper CMP in future super low-k (k<2) integration because the stress-free characteristics of copper EP are compatible with the poor mechanical properties of low-k materials. However, like electroplating techniques, copper electropolishing techniques result in the formation of metal layers having a non-uniform thickness caused by non-uniform current distribution in the electrochemical plating tank. As shown in FIG. 1A, when an anode/wafer 60 having a metal layer 60a is subjected to an electropolishing process in a conventional electroplating apparatus 10, the non-uniform current distribution in the plating tank 12 results in a cathode 65 having a layer of electroplated metal 66 with excess metal 67 at the edge regions. The metal layer 60a of the anode/wafer 60 has thin edge regions 20 relative to the remaining portion of the electroplated metal 66.
In an electroplating or electropolishing process, the magnitude of the electric field is inversely proportional to the distance between the cathode and anode. Therefore, the deposition current density can be compensated for by using a stepped or non-planar electrode to enhance the plating or polishing uniformity. Accordingly, a current-leveling electrode having a stepped or non-planar profile is needed to facilitate a uniform current distribution during an electroplating or electropolishing process in order to provide an electroplating layer having a uniform thickness on a substrate.